1. Field of the Invention
The present invention relates generally to an electrically erasable and programmable non-volatile read only memory (hereinafter abbreviated as EEPROM), and more specifically, to a non-volatile semiconductor device permitting miniaturization and high density integration.
2. Description of the Background Art
FIG. 19 is a block diagram showing a conventional EEPROM, writing and erasure of information to and from which can be performed electrically.
Referring to FIG. 19, the EEPROM includes a memory cell array 50 including EEPROM cells, a row address buffer 51 for receiving an externally applied row address signal, a column address buffer 52 for receiving a column address signal, a row decoder 53 and a column decoder 54 for decoding these address signals, and for applying voltage to a word line and a bit line connected to a designated memory cell, a sense amplifier 56 for reading a signal stored in the memory cell designated by the two decoders through a Y gate 55, an output buffer 57 for outputting the read signal, and a control signal input buffer 58 for receiving an externally applied control signal to apply the same to each element of the device.
In operation, sense amplifier 56 detects a signal stored in a memory cell, and amplifies the signal to apply the amplified signal to output buffer 57. FIG. 20 is a circuit diagram showing examples of memory cell arrays 50 and Y gate 55 shown in FIG. 19.
Referring to FIG. 20, Y gate 55 includes a transistor 60 connected between an I/O line 59 and a bit lines 31, and a transistors 63 connected between a CG line 61 and a control gate line 62. A Y gate signal Y2 is applied to the gates of transistors 60 and 63. A transistor to which a Y gate signal Y1 is applied has a similar connection.
Memory cells of 4 bits are shown in memory cell array 50. One memory cell includes a memory transistors 6 having a floating gate, and a selecting transistors 3 with its gate connected to a word line 32 for applying a signal stored in memory transistor 6 to bit lines 31. Another transistor 3a has such a connection that its gate is connected to word line 32 and applies a signal from control gate line 62 to memory transistor 6.
In operation, memory transistor 6 stores a binary signal depending upon whether electrons are stored in its floating gate or not. If electrons are stored, the threshold voltage of memory transistors 6 increases. This causes memory transistor 6 to be turned off in its reading operation. If electrons are not stored, the threshold voltage of memory transistor 6 is pulled to negative. This results in turning on of memory transistor 6 in its reading operation.
Voltage for use in reading from sense amplifier 56 is applied to bit line 31 through transistor 60, and the voltage is further applied to memory transistor 6 through selecting transistor 3. This enables detection in the sense amplifier as to whether or not current flows through memory transistor 6, and, therefore, the signals stored in the memory transistor 6 can be read out.
FIG. 21 is a view showing a conventional EEPROM having a floating gate.
(A) is a top plan view, and (B) is a sectional view taken along line B--B in (A). Description will be provided on the structure of the EEPROM in conjunction with FIG. 13.
The EEPROM includes a memory transistor 6 and a selecting transistor 3 formed on a main surface of a P type silicon semiconductor substrate 20. Memory transistor 6 includes a tunnel impurity diffusion layer 9 which is to be a drain region formed on the main surface of P type silicon substrate 20, a source region 2, a thin tunnel insulating film 16 formed in a prescribed region on tunnel impurity diffusion, layer 9, a floating gate 14 of polysilicon formed in a region including at least tunnel insulating film 16 on P type silicon substrate 20 with an insulating film therebetween, and a control gate 7 formed on floating gate 14 with an interlayer silicon oxide film 15 therebetween. Control gate 7 and floating gate 14 form capacitance in their overlapped region using interlayer silicon oxide film 15. Tunnel impurity diffusion layer 9 connected to floating gate 14 and an impurity diffusion layer for connection 5 forms capacitance in the region in which tunnel insulating film 16 is formed, using tunnel insulating film 16. Furthermore, there exists capacitance formed by floating gate 14 and semiconductor substrate 20 in the region other than tunnel insulating film 16.
Floating gate 14 stores electric charges. Discharge/injection of electric charges takes place between floating gate 14 and the tunnel impurity diffusion layer 9 through tunnel insulating film 16 in accordance with voltage difference between the control gate 7 and impurity diffusion layer for connection 5 region. Selecting transistor 3 includes impurity diffusion layer for connection 5 and a drain region 1 formed a distance apart from each other on the main surface of semiconductor substrate 20, and a selecting gate electrode 4 to be a word line formed therebetween. A selecting gate silicon oxide film 13 is formed between selecting gate electrode 4 and the main surface of semiconductor substrate 20. Drain region 1 is connected to bit line 31 through a contact hole.
Selecting transistor 3 is turned on/off in response to a signal applied through selecting gate electrode 4. Information which is stored in memory transistor 6 connected to selecting transistor 3 is thus read out to bit line 31.
Now, description will be provided on the operation of the EEPROM. The EEPROM has three basic operation modes, reading, erasure, and writing. Table 1 sets forth voltages applied to the elements when informative charges are written, erased, and read to and from floating gates 14.
TABLE 1 ______________________________________ ELEMENT READ ERASE WRITE ______________________________________ SELECTING GATE 5 V V.sub.PP V.sub.PP ELECTRODE 4 CONTROL GATE 7 0 V V.sub.PP 0 V BIT LINE 31 1 V 1 V V.sub.PP SOURCE LINE 0 V 0 V FLOATING FLOATING GATE 14 V.sub.F V.sub.E V.sub.W ______________________________________
V.sub.pp represents a program voltage, V.sub.F is a potential at the time of floating, and V.sub.w and V.sub.E the potentials of floating gates 14 at the time of writing and erasure operations.
As set forth in Table 1, in erasing a memory cell, V.sub.pp is applied to selecting gate electrode 4 and control gate 7, and bit line 31 and source line 12 are grounded. In this erasure cycle, electrons are injected through tunnel insulating film 16 from impurity diffusion layer for connection 5 into floating gate 14. As a result, negative charges are accumulated on floating gate 14.
As set forth in Table 1, in a writing operation into a memory cell, V.sub.pp is applied to selecting gate electrode 4 and bit line 31. Control gate 7 is grounded, and source line 12 is held at a floating state. Then, the area between drain 1 and impurity diffusion layer for connection 5 conducts, electrons are discharged from floating gate 14 through tunnel insulating film 16 based on a principle which will be described later, and positive charges are accumulated at floating gate 14. In reading, 5V is applied to selecting gate electrode 4, 1 V is applied to bit line 31, and control gate 7 and source line 12 are grounded. The channel region 10 of the memory transistor is turned on/off in response to the potential of floating gate 14. More specifically, when the memory transistor is in the state of erasure, negative charge is accumulated on floating gate 14, and channel region 10 is therefore turned off. Conversely, when the memory transistor is in the state of data written, negative charge is not accumulated on floating gate 14, and channel region 10 is therefore turned on. In this manner, the state of the memory transistor is determined.
FIG. 22 is an equivalent circuit diagram showing the EEPROM shown in FIG. 21. C1 represents a tunnel capacitance formed in the tunnel region. C2 is a capacitance comprised of loating gate 14, control gate 7, and an interlayer silicon oxide film 15 existing therebetween. C3 is a parasitic capacitance, and is comprised of floating gate 14, tunnel impurity diffusion layer 9 formed underneath, and tunnel insulating film 16 existing therebetween. FIG. 22 (A) shows a state of an EEPROM not in operation. When in the erasure mode, for example, as set forth in Table 1, V.sub.pp is applied to control gate 7, tunnel impurity diffusion layer 9 is grounded, and an equivalent circuit at that time is as shown in FIG. 22 (B). The potential V.sub.F at that time will be represented as follows: EQU V.sub.F =C2/(C1+C2+C3).V.sub.PP ( 1)
where C2/(C1+C2+C3) is referred to as a capacitive coupling ratio, and is usually around 0.7. The size of the electric field of the tunnel insulating film and the amount of current flowing through the tunnel insulating film are represented by the following equations: EQU E.sub.OX =V.sub.F /TOX (2) EQU J=AE.sub.OX.sup.2 exp-(B/E.sub.OX) (3)
where E.sub.OX is the electric field,
T.sub.OX is the thickness of the tunnel insulating film, PA1 J is a current, and PA1 A, B are constants.
Substituting equation (2) for equation (1) with a capacitive coupling ratio of 0.7, and T.sub.OX of 10 nn results in: E.sub.OX =14 MV/cm.
Substitution of this value for equation (3) results in a sufficiently large value, J. This is because the EEPROM is in an enhancement state. Using this value, electrons are discharged/injected between floating gate 14 and impurity region 9 on the substrate through the tunnel insulating film.
Brief description has been given on a conventional EEPROM.
Now, description will be provided on a method of manufacturing the conventional EEPROM. An oxide film 74 to be tunnel insulating film 16 is formed on P type silicon substrate 20 and polysilicon 70 is deposited thereon. Resist 77 is coated on a prescribed part on polysilicon 70 (FIG. 23 (A)).
An insulating film 80 is formed on polysilicon 70 patterned into a prescribed length, and a polysilicon layer 71 is deposited on insulating films 80 and 74. Resists 78 and 79 are coated on prescribed parts on polysilicon layer 71 (FIG. 23 (B)).
Etching is performed in this state, and a polysilicon layer is patterned, which forms selecting transistor 3 and memory transistor 6 as shown in FIG. 23 (C). Selecting transistor 3 includes selecting gate 4, and selecting gate silicon oxide film 13, while memory transistor 6 includes control gate 7, interlayer silicon oxide film 15, floating gates 14 and tunnel insulating film 16. An n type impurity is introduced in this state, forming drain region 1, source region 2 and impurity diffusion layer for connection 5.
Then, drain region 1, source region 2, and metal interconnection layers 11 and 12 are formed, and an interlayer insulating film 76 is formed, covering selecting transistor 3 and memory transistor 6 (23 (D)).
FIG. 24 is an equivalent circuit diagram in the case where the conventional EEPROM cells in FIG. 13 are arranged as memory cell array 50. Selecting transistor 3a, 3b and memory transistor 6a, 6b are disposed as shown in FIG. 24.
Now, description will be provided on a conventional flash type EEPROM. FIG. 25 is a view schematically showing the structure of a conventional flash type EEPROM. Referring to FIG. 25, the conventional flash type EEPROM includes memory transistors 82a and 82b formed a distance apart from each other on the main surface of a P type semiconductor substrate 81 with an insulating film therebetween, a source region 83 formed between memory transistors 82a and 82b and on the main surface of P type semiconductor substrate 81, and the drain regions 84a and 84b formed on the side opposing to the source 83 of memory transistors 82a and 82b. Drain regions 84a and 84b are provided with metal interconnection layers. Memory transistors 82a and 82b include floating gates 85a and 85b, and control gates 86a and 86b respectively.
The operation will be described. The conventional flash type EEPROM takes advantage of an avalanche phenomenon for writing, and a tunnel phenomenon for erasures which has been described in conjunction with the operation of the EEPROM in the foregoing. Reading is conducted in a similar manner to the case of EEPROM described above. The operation of an EEPROM is disclosed in detail, for example, in U.S. Pat. No. 4,797,856, which is incorporated herein by reference.
The size of the conventional flash type EPROM can be reduced considerably like the case of a flash type EEPROM.
Such a flash type EEPROM is described in detail, for example, in "An In-System Reprogrammable 32K.times.8 CMOS Flash Memory," IEEE JOURNAL OF SOLID-STATE CIRCUIT Vol. 23, No. 5, October. 1988, or in U.S. Pat. No. 4,868,619 which is incorporated herein by reference.
Having such a configuration, a conventional EEPROM requires one selecting transistor each for one memory cell in order to write, erase and read data on a bit-unit basis. Consequently, the cell area must be expanded, thus hindering the high density integration.
In the case of a flash type EEPROM permitting higher density integration, an electrically erasable non-volatile semiconductor memory device can be provided without requiring a selecting transistor, taking advantage of avalanche phenomenon for writing. More specifically, referring to FIGS. 25A and 25B, at the time of writing data into memory transistor 82a, a pulse of about 8 V is applied to drain 84a for about 10 .mu.sec, with a high voltage of about 12 V being applied to control gate 86a, and source 83 and substrate 81 being grounded. At that time, avalanche phenomenon takes place at the end of the drain 84a of the channel portion underlying floating gate 85a, and a large amount of current flows from drain 84a to source 83 and substrate 81. At that time, a part of electrons is attracted into floating gate 85a by the potential of floating gate 85a induced by the potential of control gate 86 a. This writing operation results in inefficient writing and large power consumption. Also, without a selecting transistor, at the time of erasing data by means of tunnel phenomenon between floating gate 85a and source 83, certain means is necessary for preventing memory transistor 82a from attaining a depletion state, in other words an excessive erasure state resulting in difficulty in the associated circuitry.
As a result, strict control of conditions in the manufacture will be needed and a special complicated erase method is used to avoid overerase. Typically several erasure pulses are generated, and additionally, memory test is checked for providing a device with balanced characteristics. As a result, the cost of EEPROM is pushed up.